最近的实验要用到 risc-v smepmp extension, 研究了一下怎样改 CPU 和 SoC。
Hardware
- 参考配置
parser.set_defaults(
cpu_type="vexiiriscv",
cpu_variant="debian",
update_repo = "no",
with_jtag_instruction = True,
with_sdcard = True,
with_spi_flash = True,
# with_ethernet = True,
)- 接入板载调试器:
soc.jtag = jtag = XilinxJTAG(XilinxJTAG.get_primitive(soc.platform.device), chain=4)
soc.comb += [
soc.cpu.jtag_reset.eq(jtag.reset),
soc.cpu.jtag_capture.eq(jtag.capture),
soc.cpu.jtag_shift.eq(jtag.shift),
soc.cpu.jtag_update.eq(jtag.update),
soc.cpu.jtag_clk.eq(jtag.tck),
soc.cpu.jtag_tdi.eq(jtag.tdi),
soc.cpu.jtag_enable.eq(True),
jtag.tdo.eq(soc.cpu.jtag_tdo),
]- 配置 openocd
adapter driver ftdi
ftdi_vid_pid 0x0403 0x6010
ftdi_channel 0
ftdi_layout_init 0x00e8 0x60eb
ftdi_tdo_sample_edge falling
reset_config none
adapter speed 5000
source [find cpld/xilinx-xc7.cfg]
source [find cpld/jtagspi.cfg]- 配置
riscv_tap.tcl
# SPDX-FileCopyrightText: 2023 "Everybody"
#
# SPDX-License-Identifier: MIT
set _CHIPNAME riscv
set _TARGETNAME $_CHIPNAME.cpu
set cpu_count 1
if [info exists env(RISCV_COUNT)] {
set cpu_count $::env(RISCV_COUNT)
}
if { [info exists TAP_NAME] } {
set _TAP_NAME $TAP_NAME
} else {
set _TAP_NAME $_TARGETNAME
}
adapter speed 500
# external jtag probe
if {$_TAP_NAME eq $_TARGETNAME} {
jtag newtap $_CHIPNAME cpu -irlen 6 -expected-id 0x10003FFF
}
for {set i 0} {$i < $cpu_count} {incr i} {
target create $_TARGETNAME.$i riscv -coreid $i -chain-position $_TAP_NAME
riscv use_bscan_tunnel 6 1
#riscv set_bscan_tunnel_ir 0x23 #In riscv-openocd upstream
}
for {set i 0} {$i < $cpu_count} {incr i} {
targets $_TARGETNAME.$i
init
halt
}
echo "Ready for Remote Connections"- 启动调试
openocd -f .\prog\kc705.cfg -c "set TAP_NAME xc7.tap" -f .\prog\riscv_tap.tcl连接方式：
riscv64-unknown-elf-gdb.exe -ex "target extended-remote localhost:3333"Software
csr 可导出为 dts
litex_json2dts_linux .\build\xilinx_kc705\csr.json > build/kc705.dts